An integrated circuit (IC) is fabricated according to a layout design usable to form a plurality of masks for selectively forming or removing various layers of features, such as active regions, gate electrodes, various layers of isolation structures, and/or various layers of conductive structures. Many fabrication processes are available to increase the spatial resolution of various layers of features and thus allow layout patterns to have a finer spatial resolution in a corresponding layout. However, many of the fabrication processes for increasing the spatial resolution of features are performed at the expense of increased complexity and resources, such as additional masks, additional exposure processes, and/or additional etching processes.